Prospects and Challenges for Sub-3nm CMOS Scaling: A Critical Review of Post-FinFET Solutions

Author(s)	Mr. Vedant Kumar Saha, Dr. Sapan Kumar Saha
Country	India
Abstract	FinFET technology, which offers better gate control than planar MOSFETs, enabled CMOS scaling from 22nm to 5nm. However, FinFET encounters basic electrostatic, parasitic, and manufacturing constraints that deteriorate Power-Performance-Area (PPA) scaling as the industry moves toward sub-3nm nodes. In order to control short-channel effects and replace planar MOSFET, FinFET was introduced at the 22nm node. Up to 5nm, it served as the workhorse for TSMC, Samsung, and Intel. However, FinFET encounters basic manufacturing and physical constraints when scaling gets closer to sub-3nm. This paper explores those limits and evaluates upcoming device technologies like GAA-FET and CFET that can extend Moore’s Law beyond FinFET. This study examines the main drawbacks of FinFET below 3nm and compares two new device architectures. At the same time, the Synopsys Sentaurus Technology Computer-Aided Design (TCAD) simulation package is used to do the quantitative evaluation and comparative study of the FinFET and Gate-All-Around (GAA) Nanosheet FET at the 3-nm technology node.
Keywords	FinFET, Gate-All-Around, Nanosheet, CFET, Short-Channel Effects, Sub-3nm.
Field	Physics > Nano Technology / Nuclear
Published In	Volume 17, Issue 8, August 2026
Published On	2026-08-04

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