A Lightweight Confidence-Guided Adaptive Sobel FPGA Implemented Architecture with Spatially Supported Edge Decisions

Kuldeep Singh; Vinod Kumar; Ajay Kumar; Rhythem Gupta; Govind Saini

A Lightweight Confidence-Guided Adaptive Sobel FPGA Implemented Architecture with Spatially Supported Edge Decisions

Author(s)	Dr. Kuldeep Singh, Dr. Vinod Kumar, Dr. Ajay Kumar, Ms. Rhythem Gupta, Mr. Govind Saini
Country	India
Abstract	In the implementation of the emerging embedded computer-vision systems the real-time edge detection is becoming an essential preprocessing operation. The fixed-threshold Sobel realizations have advantages because they have simple arithmetic circuits with low complexity, but it is difficult for a single threshold to explicitly differentiate between strong responses, uncertain weak responses, and its background. In this paper a confidence-aware adaptive Sobel edge-detection architecture is presented and realized on FPGA with timing-closed performance and physically validated FPGA realization on a Zynq-7000 XC7Z020 Zed-Board. The architecture basically used a method that combines a conventional 3×3 Sobel gradient operator with three-level image recognition metric as confidence classification and surrounding neighborhood supported approval of intermediate-gradient responses. The recommended hardware architecture is based on utilization of synchronous dual-port frame buffers, a pipelined processing or display path, and a mixed-mode clock manager (MMCM)-derived VGA pixel clock. The behavioral verification experiment is executed for 1,679,998 pixel-clock samples, 2,099 raster lines, and four frame starts with zero assertion errors and zero monitor warnings; the calculated pixel-clock frequency was 25.174825 MHz. The post-synthesis timing shows WNS = −0.443 ns and TNS = −2.069 ns, whereas the routed implementation achieved improvement in WNS = +0.022 ns, TNS = 0 ns, and WHS = +0.064 ns. The implemented design utilizes 1,563 LUTs, 1,284 flip-flops, one RAMB36 and two RAMB18 blocks, and one MMCM. The total post-route analysis estimates the on-chip power of 0.254 W. The results obtained shows the practical hardware implementation feasibility and timing closure with the generated bitstream. The target hardware was programmed on the Zed-Board and shows validation using an externally connected VGA display. The expected three-panel display—input in grayscale, conventional Sobel as baseline, and confidence-aware adaptive as output—was reported, and a multiple SW [7:0] switch configurations was exercised and produced repeatable threshold-dependent changes in the detected-edge maps. The observed results establish the simulation correctness, timing closure, bitstream generation, and physical on-board VGA functionality test for the desired system.
Keywords	Adaptive edge detection, confidence-aware processing, FPGA, Sobel operator, Zynq-7000, VGA, timing closure, embedded vision
Field	Computer > Electronics
Published In	Volume 17, Issue 10, October 2026
Published On	2026-10-29

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International Journal of Technology and Applied Science

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A Lightweight Confidence-Guided Adaptive Sobel FPGA Implemented Architecture with Spatially Supported Edge Decisions

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